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An Integrated Approach to Transactional Memory on Multi and Many-core Computers
MULTIPROG 2013 Workshop - Submit your work on Transactional Memory
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Circuit Design of a Dual-Versioning L1 Data Cache for Optimistic Concurrency
Azam Seyedi, Adria Armejach, Adrián Cristal, Osman S. Unsal, Ibrahim Hur, Mateo Valero
, Proceedings of the 21st Great Lakes Symposium on Very Large Scale Integration (GLSVLSI'11)
(Best Paper Award
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