AMD and the VELOX research project
AMD's Operating System Research Center plays a central role in the EU-funded VELOX project, which targets an integrated approach to transactional memory (TM) on multi and many-core computers.
AMD OSRC has two main objectives in the VELOX Project: to provide partners with support for verifying the feasibility of implementation proposals from an industry point-of-view, and to verify its own hardware-transactional-memory proposal (AMD's ASF). Hardware support for speeding up critical paths in STM proposals and support for
hybrid software-hardware solutions (HyTM) as targeted with ASF are both key motivations for AMD's participation.
HTM is not available for current industry Architectures, but there is increasing demand for a solution to relocate the costly bookkeeping to dedicated silicon.
PTLsim is a cycle accurate x86 microprocessor simulator and virtual machine for the x86 and x86-64 instruction sets. PTLsim will included in an integrated VELOX Project demonstrator. AMD is working to extend PTLsim's memory module to correspond better to current AMD multicore systems. When this process is complete, other more versatile memory modules may be used together with PTLsim's core, such as the VELOX module that is currently being developed at Chalmers University of Technology.
Alternatively, the refactored memory module in PTLsim may be further developed and extended to more accurately model a HyperTransport-connected NUMA system.
More information at the AMD coorporate blogs: