The Multiprog 2013 website is now available at http://multiprog.ac.upc.edu/. Please consider submitting your work on Transactional Memory to the workshop. The theme of the workshop is hardware and software support for improving programmability on multi-core architectures and is a good fit for TM-related research.
PLDI Tutorial Slides are now available for download
Tutorial presentations are available for download
VELOX Team relax and pose for a post-review photo.
The VELOX Project achieved top marks in the official final review held at European Commission offices in Brussels. Team members Christof Fetzer (TUD), Pascal Felber (UNINE), Gina Alioto (BSC), Osman Unsal (BSC) and Per Stenström (CHALMERS) presente
The VELOX Stack was once again featured at a TM-star-studded event, the Annual EuroTM (COST Action) Plenary Meetings held in Paris, France ( http://www.eurotm.org/1st-plenary-meeting-in-paris/program). VELOX Team member Patrick Marlier of the University of Neuchâtel presented the VELOX Stack in its entirety while Pascal Felber (also of Neuchâtel) spoke about the impact of the project on the future of TM. Osman Unsal of the Barcelona Supercomputing Center discussed VELOX FPGA achievements, and Guy Korland of Tel Aviv University talked about his Java contributions to the stack.
VELOX Stack presented at the HiPEAC Multi-core Architecture Cluster Meeting in Chamonix, France
This most recent HiPEAC cluster meeting offered four interesting highlights of ongoing/just concluded multicore architecture projects, including VELOX as presented by Osman Unsal of the Barcelona Supercomputing Center.
More information about the cluster and the meeting can be found at: http://www.hipeac.net/Multi-core_architecture
CACM publishes informed rebuttal: "Why STM Can Be More than a Research Toy"
Communications of the ACM is publishing this coming month the article "Why STM Can Be More than a Research Toy" by A. Dragojevic, P. Felber, V. Gramoli and R. Guerraoui. This article demonstrates that STM finally wins its spurs by outperforming sequential applications with only four CPU cores. The publication responds to a paper invited about two years ago in the same venuethat suggested the confinement of STM to a research toy by questioning its ability to leverage multicore architectures.
VELOX paper wins "Best Paper Award" at ICPE2011 Conference
Gokçen Kestor (BSC) receives the "Best Paper Award"
Release 3 of the VELOX Integrated Stack available for download
VELOX Project to present tutorial at PLDI 2011
The tutorial is targeted toward (i) Software and Hardware developers and researchers that are not familiar with Transactional Memory (TM) that are curious to learn what TM can offer, or (ii) developers and researchers that have a general understanding of TM that would like to start developing code or engage in research using TM.
For the latest information regarding this tutorial, visit the tutorial website.